Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring.
One important process requiring careful inspection is photolithography, wherein masks or “reticles”, are used to transfer circuitry patterns to semiconductor wafers. Typically, the reticles are in the form of pattern chrome over a transparent substrate, and a series of such reticles are employed to project the patterns on to the wafer in a preset sequence. Each photolithographic reticle includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each reticle in the series is used to transfer its corresponding pattern onto a photosensitive layer (i.e., a photoresist layer) which has been previously coated on a layer, such as a polysilicon or metal layer, formed on the silicon wafer. The transfer of the reticle pattern onto the photoresist layer is conventionally performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the reticle to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
It should be appreciated that any defect on the reticle, such as an extra or a missing chrome may transfer onto the fabricated wafer in a repeated manner. Thus, any defect on the reticle would drastically reduce the yield of the fabrication line. Therefore, it is of utmost importance to inspect the reticles and detect any defects thereupon. The inspection is generally performed by an optical system, such as the RT43200™ or ARIS-i™ reticle inspection systems available from Applied Materials of Santa Clara, Calif.
Basically, three inspection methods are available, die-to-database, die-to-die, and reflected-to-transmitted. In the mask shop, i.e., where the masks and reticles are produced, typically the die-to-database method is used, where the inspection system is used to scan the mask and compared the obtained image to the database used to create the mask. Any difference between the image and the database is flagged as a suspect location. On the other hand, in the wafer fabrication plant, ‘the die-to-die method is more prevalent, where the inspection system is used to Scan the mask and compare the image obtained from one die on the mask to another die on the same mask. Any difference between both images is flagged as a suspect location. In a reflected-to-transmitted inspection, the system is used to scan the’, mask, and an image obtained from transmitted light is compared to image obtained from reflected. light. In either case, the resulting-output is an indication of all the locations on the reticle suspected to have a defect thereupon. Such an output is generally known in the industry as a defect map.
Another aspect of semiconductor wafer fabrication is the design rule. These design rules define, e.g., the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. The design rule limitation is referred to as the critical dimension (“CD”), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device. The CD for most ultra large scale integration applications is on the order of a fraction of a micron.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, measurement of reticle features is becoming increasingly important, since even small deviations of line widths from design dimensions may adversely affect the performance of the finished semiconductor device. Conventionally, a critical dimension scanning electron microscope (CDSEM), such as the VeraSEM™, available from Applied Materials of Santa Clara, Calif., is used to measure line widths. However, due to the slow operation of CD-SEM's, only selected locations (generally about 25) are examined, and statistical analysis is used to determine the quality of the CD over the entire reticle or wafer. The sample sites are usually located in areas on the reticle likely to have deviations, and are selected based on the experience of the user and/or statistical techniques.
As can be appreciated, the usefulness of CD-SEM inspection of reticle CD depends, to a great extent, on the ability to predict which sites on the reticle contain variations. Moreover, the number of CD-SEM sample sites is typically limited, since inspection time for each site is considerable. Thus, significant but. unobvious CD errors may go unnoticed during inspection, such as “global” errors causing CD variations across the reticle, which indicate reticle manufacturing problems; e.g., a greater CD deviation in the features in the center of the reticle than in features at the perimeter of the reticle.
Recently, Applied Materials has introduced in its RT-8000 ml series and ARIS-i reticle inspection systems a new feature, called Line Width Error Detector (“LWED”). In addition to the normally reported defects, as explained above, this feature allows the system to report another type of defect, namely line width errors. Specifically, the LWED compares the feature sizes of the reticle under inspection with feature sizes from a design database to determine any width deviation from the data base. An example of a feature width difference defect that can be discovered by the LWED is shown in FIG. 1. Any deviations discovered by the LWED are reported on the defect map as locations suspected of having defects thereupon.
It can be appreciated from the above that the LWED somewhat bridges the previously distinct issues of defect detection and CI) inspection. Such bridging may be very beneficial to the wafer fabrication process. Specifically, perhaps the biggest technology issue in advancing optical lithography to smaller design rules is the Mask Error Factor ‘MEF’ a.k.a. mask error enhancement factor “MEEF”. This factor accounts for the observation that small variations in CD on the mask can cause large variations on the wafer at sub-wavelength resolution. Therefore, there exists a need for a simple, fast, and cost-effective methodology for inspection of CD errors over the entire reticle, in addition for inspecting the reticle for defects.